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TC500/A/510/514
Precision Analog Front Ends
Features
* Precision (up to 17-bits) A/D Converter "Front End" * 3-Pin Control Interface to Microprocessor * Flexible: User Can Trade-off Conversion Speed for Resolution * Single Supply Operation (TC510/TC514) * 4 Input, Differential Analog MUX (TC514) * Automatic Input Voltage Polarity Detection * Low Power Dissipation: - (TC500/TC500A): 10m - (TC510/TC514): 18m * Wide Analog Input Range: 4.2V (TC500A/TC510) * Directly Accepts Bipolar and Differential Input Signals
Package Types
16-Pin SOIC 16 Pin-PDIP
CINT VSS CAZ BUF ACOM CREF- CREF+ VREF
1 2 3 4 5 6 7 8 16 VDD 15 DGND TC500/ 14 CMPTR OUT TC500A 13 B COE TC500/ 12 A TC500A 11 VIN+ CPE 10 VIN- 9
VREF+
24-Pin SOIC 24-Pin PDIP
VOUTCINT CAZ BUF ACOM CREFCREF+ VREF+ VREF1 2 3 4 5 6 7 8 9 24 CAP23 DGND 22 CAP+ 21 VDD 20 OSC
Applications
* Precision Analog Signal Processor * Precision Sensor Interface * High Accuracy DC Measurements
Device Selection Table
Part Number TC500ACOE TC500ACPE TC500COE TC500CPE TC510COG TC510CPF TC514COI TC514CPJ Package 16-Pin SOIC (Wide) 16-Pin PDIP (Narrow) 16-Pin SOIC (Wide) 16-Pin PDIP (Narrow) 24-Pin SOIC (Wide) 24-Pin PDIP (Narrow) 28-Pin SOIC (Wide) 28-Pin PDIP (Narrow) Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C
TC510COG 19 CMPTR OUT TC510CPF 18 A
17 B 16 VIN+ 15 VIN14 N/C 13 N/C
N/C 10 N/C 11 N/C 12
28-Pin SOIC 28-Pin PDIP
VOUTCINT CAZ BUF ACOM CREFCREF+ VREFVREF+
1 2 3 4 5 6 7 8 9 28 CAP27 DGND 26 CAP+ 25 VDD 24 OSC 23 CMPTR OUT
TC514COI TC514CPJ
22 A 21 B 20 A0 19 A1 18 CH1+ 17 CH2+ 16 CH3+ 15 CH4+
CH4- 10 CH3- 11 CH2- 12 CH1- 13 N/C 14
2002 Microchip Technology Inc.
DS21428B-page 1
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TC500/A/510/514
General Description
TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17-bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17-bits. The TC510 adds an onboard negative power supply converter for single supply operation. The TC514 adds both a negative power supply converter and a 4 input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5XX through four phases of conversion: Auto Zero, Integrate, De-integrate and Integrator Zero. During the Auto Zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the Integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the De-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its on-board timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator Zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17bits), superior 50Hz/60Hz noise rejection, low power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds.
Typical Application
Control Logic RINT CREF A0 A1 CREF+ CH1+ CH2+ CH3+ CH4+ CH1CH2CH3CH4ACOM SWI VSS OSC SW1 Analog Switch Control Signals VOUTCAP- CAP+ VSS COUT1.0F (TC500 TC500A) A B Control Logic Phase Decoding Logic DGND SWR SWR DIF. MUX (TC514) SWI SWRI- SWRIVREF+ VREFCAZ CREFBuffer - + + BUF CAZ Integrator CMPTR 1 CMPTR 2 + - - + CINT CINT A 0 0 1 1 B 0 1 0 1 Converter Sate Zero Integrator Output Auto-Zero Signal Integrate Deintegrate TC500 TC500A TC510 TC514 Level Shift CMPTR Output
SWZ
SWIZ SWZ SWRI+ SWRIPolarity Detection
DC-TO-DC Converter (TC510 & TC514)
1.0F
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TC500/A/510/514
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
TC510/TC514 Positive Supply Voltage (VDD to GND) ......................................... +10.5V TC500/TC500A Supply Voltage (VDD to V SS) .............................................. +18V TC500/TC500A Positive Supply Voltage (VDD to GND) ............................................ +12V TC500/TC500A Negative Supply Voltage (VSS to GND)................................................-8V Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS Logic Input Voltage...............VDD +0.3V to GND - 0.3V Voltage on OSC: ........................... -0.3V to (VDD +0.3V) for V DD < 5.5V Ambient Operating Temperature Range: ................................................................ 0C to +70C Storage Temperature Range: ............. -65C to +150C
TC500/A/510/514 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = 5V unless otherwise specified. CAZ = CREF = 0.47F.
Symbol Analog Resolution ZSE ENL Zero Scale Error with Auto Zero Phase End Point Linearity 60 -- -- -- -- -- -- ZS TC SYE FS TC Zero-Scale Temp. Coefficient Full-Scale Symmetry Error (Roll-Over Error) Full-Scale Temperature Coefficient -- -- -- -- -- -- 0.005 -- 0.003 -- -- 0.01 -- -- 0.005 0.003 0.015 0.010 0.008 0.005 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.005 0.003 0.015 0.010 -- -- 1 0.03 10 -- 0.012 0.009 0.060 0.045 -- -- 2 -- -- V % F.S. % F.S. % F.S. % F.S. % F.S. V/C % F.S. Note 1 TC500/510/514 TC500A TC500/510/514, Note 1, Note 2, TC500A TC500/510/514, Note 1, Note 2 TC500A Over Operating Temperature Range Note 3 Parameter Min TA = +25C Typ Max TA = 0C to 70C Min Typ Max Unit Test Conditions
NL
Best Case Straight Line Linearity
ppm/C Over Operating Temperature Range; External Reference TC = 0 ppm/C pA VIN = 0V
IIN
Input Current
--
6
--
--
--
--
Note 1: Integrate time 66msec, auto zero time 66msec, VINT (peak) 4V. 2: End point linearity at 1/4, 1 /2, 3/4 F.S. after full-scale adjustment. 3: Roll-over error is related to C INT, CREF, C AZ characteristics.
2002 Microchip Technology Inc.
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TC500/A/510/514
TC500/A/510/514 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = 5V unless otherwise specified. CAZ = CREF = 0.47F.
Symbol Parameter Min Analog (Continued) VCMR Common Mode Voltage Range Integrator Output Swing Analog Input SignalRange VREF Digital VOH VOL VIH VIL IL tD Comparator Logic 1, Output High Comparator Logic 0, Output Low Logic 1, Input High Voltage Logic 0, Input Low Voltage Logic Input Current Comparator Delay 4 -- 3.5 -- -- -- -- -- -- -- -- 2 -- 0.4 -- 1 -- -- 4 -- 3.5 -- -- -- -- -- -- -- 0.3 3 -- -- 0.4 -- 1 V V V V A sec Logic 1 or 0 ISOURCE = 400A ISINK = 2.1mA Voltage Reference Range VSS +1.5 VSS +0.9 VSS +1.5 VSS +1 -- -- -- -- VDD - 1.5 VSS + 1.5 VDD - 0.9 VSS +0.9 -- -- -- -- VDD - 1.5 VSS +0.9 VSS +1.5 VDD - 1 V V V V ACOM = GND = 0V VREF - VREF+ TA = +25C Typ Max TA = 0C to 70C Min Typ Max Unit Test Conditions
VDD - 1.5 VSS +1.5 VDD - 1 VSS +1
Multiplexer (TC514 Only) Maximum Input Voltage RDSON Drain/Source ON Resistance -2.5 -- -- 6 2.5 10 -2.5 -- -- -- 2.5 -- V k VDD = 5V VDD = 5V
Power (TC510/TC514 Only) IS PD VDD ROUT Supply Current Power Dissipation Positive Supply Operating Voltage Range Operating Source Resistance Oscillator Frequency IOUT Maximum Current Out -- -- 4.5 -- -- -- 1.8 18 -- 60 100 -- 2.4 -- 5.5 85 -- -10 -- -- 4.5 -- -- -- -- -- -- -- -- -- 3.5 -- 5.5 100 -- -10 mA mW V kHz mA IOUT = 10mA (Note 3) VDD = 5V VDD = 5V, A = 1, B = 1 VDD = 5V
Power (TC500/TC500A Only) IS PD VDD VSS Supply Current Power Dissipation Positive Supply Operating Range Negative Supply Operating Range -- -- 4.5 -4.5 1 10 -- -- 1.5 -- 7.5 -7.5 -- -- 4.5 - 4.5 -- -- -- -- 2.5 -- 7.5 -7.5 mA mW V V VS = 5V, A = B = 1 VDD = 5V, VSS = -5V
Note 1: Integrate time 66msec, auto zero time 66msec, VINT (peak) 4V. 2: End point linearity at 1/4, 1 /2, 3/4 F.S. after full-scale adjustment. 3: Roll-over error is related to C INT, CREF, C AZ characteristics.
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TC500/A/510/514
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number (TC500, TC500A) 1 2 3 4 5 6 7 8 9 10 11 12 13
PIN FUNCTION TABLE
Pin Number (TC510) 2 3 4 5 6 7 8 9 15 16 18 17 Pin Number (TC514) 2 3 4 5 6 7 8 9 Not Used Not Used 22 21 Symbol CINT VSS CAZ BUF ACOM CREFCREF+ VREFVREF+ VINVIN + A B Description Integrator output. Integrator capacitor connection. Negative power supply input (TC500/TC500A only). Auto Zero input. The Auto Zero capacitor connection. Buffer output. The Integrator capacitor connection. This pin is grounded in most applications. It is recommended that ACOM and the input common pin (Ven- or CHn-) be within the analog common mode range (CMR). Input. Negative reference capacitor connection. Input. Positive reference capacitor connection. Input. External voltage reference (-) connection. Input. External voltage reference (+) connection. Negative analog input. Positive analog input. Input. Converter phase control MSB. (See input B.) Input. Converter phase control LSB. The states of A, B place the TC5XX in one of four required phases. A conversion is complete when all four phases have been executed: Phase control input pins: AB = 00: Integrator Zero 01: Auto Zero 10: Integrate 11: De-integrate
Not Used Not Used
14
19
23
CMPTR Zero crossing comparator output. CMPTR is HIGH during the Integration phase OUT when a positive input voltage is being integrated and is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on CMPTR signals the processor that the De-integrate phase is completed. CMPTR is undefined during the Auto Zero phase. It should be monitored to time the Integrator Zero phase. DGND VDD CAP+ CAPVOUTInput. Digital ground. Input. Power supply positive connection. Input. Negative power supply converter capacitor (+) connection. Input. Negative power supply converter capacitor (-) connection. Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. Oscillator control input. The negative power supply converter normally runs at a frequency of 100kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and VDD (see Section 9.0, Typical Characteristics Curves). Positive analog input pin. MUX channel 1. Negative analog input pin. MUX channel 1. Positive analog input pin. MUX channel 2. Negative analog input pin. MUX channel 2. Positive analog input pin. MUX channel 3. Negative analog input pin. MUX channel 3. Positive analog input pin. MUX channel 4. Negative analog input pin. MUX channel 4 Multiplexer input channel select input LSB (see A1). Multiplexer input channel select input MSB. Phase control input pins: A1, A0 = 00 = Channel 1 01 = Channel 2 10 = Channel 3 11 = Channel 4
15 16
23 21 22 24 1
27 25 26 28 1
20
24
OSC
18 13 17 12 16 11 15 10 20 19
CH1+ CH1CH2+ CH2CH3+ CH3CH4+ CH4A0 A1
2002 Microchip Technology Inc.
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TC500/A/510/514
3.0
3.1
DETAILED DESCRIPTION
Dual Slope Conversion Principles
the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (1/T) averaged over a period (T) is zero. Integrating converters often establish the integration period to reject 50/60Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 3-1). Normal mode rejection is limited in practice to 50 to 65dB, since the line frequency can deviate by a few tenths of a percent (Figure 3-2).
Actual data conversion is accomplished in two phases: input signal Integration and reference voltage De-integration. The integrator output is initialized to 0V prior to the start of Integration. During Integration, analog switch S1 connects VIN to the integrator input where it is maintained for a fixed time period (TINT). The application of VIN causes the integrator output to depart 0V at a rate determined by the magnitude of VIN and a direction determined by the polarity of VIN. The De-integration phase is initiated immediately at the expiration of TINT. During De-integration, S1 connects a reference voltage (having a polarity opposite that of VIN) to the integrator input. At the same time, an external precision timer is started. The De-integration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0V. When this occurs, the precision timer is stopped. The De-integration time period (TDEINT), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage (see Figure 3-3). A simple mathematical equation relates the Input Signal, Reference Voltage and Integration time:
FIGURE 3-1:
INTEGRATING CONVERTER NORMAL MODE REJECTION
Normal Mode Rejection (dB)
30
T = Measurment Period
20
10
0 0.1/T
1/T Input Frequency
10/T
EQUATION 3-1:
1 RINTCINT Where: VREF = Reference Voltage TINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) For a constant VIN: TINT 0 VIN(T)DT = VREFTDEINT RINTCINT
FIGURE 3-2:
80
Normal Mode Rejeciton (dB)
LINE FREQUENCY DEVIATION
70
t = 0.1 sec
60 50 40 30
DEV SIN 60 p t (1 100 ) 60 p t (1 DEV) 100 DEV = Deviation from 60Hz t = Integration Period
EQUATION 3-2:
TDEINT VIN = V REF TINT The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. Integrating converters provide inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of
Normal Mode = 20 LOG REJECTION
20 0.01 0.1 1.0 Line Frequency Deviation from 60 Hz (%)
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TC500/A/510/514
FIGURE 3-3: BASIC DUAL SLOPE CONVERTER
CINT RINT Integrator - + S1 + Phase Control VINT -
TC510
Comparator CMPTR Out
Analog Input (VIN)
REF VOLTAGE Switch Driver Polarity Control Control Logic
A VSUPPLY VINT
B I/O
Integrator Output
VIN VREF VIN 1/2 VREF
Microcomputer ROM RAM Timer Counter
TINT
TDEINT
2002 Microchip Technology Inc.
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TC500/A/510/514
4.0 TC500/A/510/514 CONVERTER OPERATION
The internal analog switch status for each of these phases is summarized in Table 4-1. This table references the Typical Application.
The TC500/A/510/514 incorporates an Auto Zero and Integrator phase in addition to the input signal Integrate and reference De-integrate phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: 1. 2. 3. 4. Auto Zero Input signal integration Reference deintegration Integrator output zero
TABLE 4-1:
INTERNAL ANALOG GATE STATUS
SWI Closed Closed* Closed Closed Closed Closed SWR+ SWRSWZ Closed SWR Closed SW1 Closed SWIZ
Conversion Phase Auto Zero (A = 0, B = 1) Input Signal Integration (A = 1, B = 0) Reference Voltage De-integration (A =1, B = 1) Integrator Output Zero (A = 0, B = 0) Note:
*Assumes a positive polarity input signal. SW-RI would be closed for a negative input signal.
4.1
Auto Zero Phase (AZ)
4.3
During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the C AZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages.
Reference Voltage De-integration Phase (DINT)
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage.
4.4
Integrator Output Zero Phase (IZ)
4.2
Analog Input Signal Integration Phase (INT)
The TC5XX integrates the differential voltage between the (V IN+) and (VIN-) inputs. The differential voltage must be within the device's Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity.
This phase ensures the integrator output is at 0V when the Auto Zero phase is entered and that only system offset voltages are compensated. This phase is used at the end of the reference voltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the Auto Zero capacitor (CAZ) must be about 2 to 3 times the value of the Integration capacitor (CINT) to reduce the effects of charge sharing. The Integrator Output Zero phase should be programmed to operate until the output of the comparator returns "HIGH". The overall timing system is shown in Figure 4-1.
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TC500/A/510/514
FIGURE 4-1:
TTIME Converter Status Integrator 0 Voltage VINT Comparator Delay Auto-Zero Integrate Full Scale Input Reference De-integrate Overshoot Integrator Output Zero
TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING
Comparator Output
Undefined
0 For Negative Input 1 For Postive Input
A AB Inputs B Controller Operation
A=0 B=1
A=1
A=1 B=1
A=0 B=0
B=0
Begin Conversion with Auto-Zero Phase
Time Input Integration Phase Sample Input Polarity TINT
Capture De-integration Time
Integrator Output Zero Phase Complete
Ready for Next Conversion (Auto-Zero is Idle State)
Typically = TINT (Positive Input Shown)
Comparator Delay + Processor Latency
Minimizing Overshoot will Minimize I.O.Z. Time
Notes: The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text).
2002 Microchip Technology Inc.
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TC500/A/510/514
5.0
5.1
ANALOG SECTION
Differential Inputs (VIN+, VIN-)
The difference in reference for (+) or (-) input voltages will cause a rollover error. This error can be minimized by using a large reference capacitor in comparison to the stray capacitance.
The TC5XX operates with differential voltages within the input amplifier Common mode range. The amplifier Common mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this Common mode voltage range, Common mode rejection is typically 80dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either supply. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst case condition exists, for example, when a large, positive Common mode voltage, with a near full scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced. The integrator output can swing within 0.9V of either supply without loss of linearity.
5.4
Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5XX operating phase. The A, B inputs are normally driven by a microprocessor I/O port or external logic.
5.5
Comparator Output
By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. The comparator output is HIGH for positive signals and LOW for negative signals during the signal integrate phase (see Figure 5-1). During the reference de-integrate phase, the comparator output will make a HIGH-to-LOW transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. The internal comparator delay is 2sec, typically. Figure 5-1 shows the comparator output for large positive and negative signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If Common mode noise is present, the comparator can switch several times during the beginning of the signal integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. The comparator output is undefined during the Auto Zero phase and is used to time the Integrator Output Zero phase. (See Section 7.6, Integrator Output Zero Phase).
5.2
Analog Common
Analog common is used as VIN return during system zero and reference de-integrate. If VIN- is different from analog common, a Common mode voltage exists in the system. This signal is rejected by the excellent CMR of the converter. In most applications, VIN- will be set at a fixed known voltage (i.e., power supply common). A Common mode voltage will exist when VIN- is not connected to analog common.
5.3
Differential Reference (VREF+, VREF-)
The reference voltage can be anywhere within 1V of the power supply voltage of the converter. Rollover error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes.
FIGURE 5-1:
COMPARATOR OUTPUT
Signal Integrate Integrator Output
Reference Deintegrate Zero Crossing
Signal Integrate
Reference De-integrate
Integrator Output Zero Crossing Comparator Output
Comparator Output A. Positive Input Signal
B. Negative Input Signal
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TC500/A/510/514
6.0
6.1
TYPICAL APPLICATIONS
Component Value Selection
TABLE 6-1:
Conversions Per Second >7 2 to 7 2 or less Note:
CREF AND C AZ SELECTION
Typical Value of CREF, CAZ (F) 0.1 0.22 0.47 Suggested* Part Number SMR5 104K50J01L4 SMR5 224K50J02L4 SMR5 474K50J04L4
The procedure outlined below allows the user to arrive at values for the following TC5XX design variables: 1. 2. 3. 4. Integration Phase Timing Integrator Timing Components (RINT, CINT) Auto Zero and Reference Capacitors Voltage Reference
Manufactured by Evox-Rifa, Inc.
6.6
6.2
Select Integration Time
Calculate Integrating Capacitor (CINT)
Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection.
6.3
DINT and IZ Phase Timing
The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI). Using the 20A buffer maximum output current, the value of the integrating capacitor is calculated using the following equation.
The duration of the DINT phase is a function of the amount of voltage stored on the integrator during TINT and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX) /2).
EQUATION 6-2:
(TINT) (20 x 10 -6) CINT = Where: TINT = Integration Period VS = IVDDI or IVSSI, whichever is less (TC500/A VS = IVDDI (TC510, TC514) It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such dielectic. Polyester and Polybicarbonate capacitors may also be used in less critical applications. Table 6-2 summarizes recommended capacitors for CINT. (VS - 0.9) F
6.4
Calculate Integrating Resistor (RINT)
The desired full scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20A. The value of RINT is therefore directly calculated in the following equation:
EQUATION 6-1:
RINT(in M) = Where: VIN(MAX) = Maximum input voltage (full count voltage) RINT = Integrating Resistor (in M) For loop stability, RINT should be 50k. VIN(MAX) 20
TABLE 6-2:
RECOMMENDED CAPACITOR FOR CINT
Suggested Part Number* SMR5 104K50J01L4 SMR5 224K50J02L4 SMR5 334K50J03L4 SMR5 474K50J04L4
Value 0.1 0.22 0.33 0.47 Note:
Manufactured by Evox-Rifa, Inc.
6.5
Select Reference (CREF) and Auto Zero (C AZ) Capacitors
6.7
Calculate VREF
CREF and C AZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value C REF must be. Recommended capacitors for CREF and CAZ are shown in Table 6-1. Larger values for CAZ and C REF may also be used to limit rollover errors.
The reference deintegration voltage is calculated using the following equation:
EQUATION 6-3:
VREF = (VS - 0.9) (CINT) (RINT) 2(RINT) V
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TC500/A/510/514
7.0
7.1
DESIGN CONSIDERATIONS
Noise
7.4
Input Signal Integrate Phase
The threshold noise (NTH) is the algebraic sum of the integrator noise and the comparator noise. This value is typically 30V. Figure 7-1 shows how the value of the reference voltage can affect the final count. Such errors can be reduced by increased integration times, in the same way that 50/60Hz noise is rejected. The signalto-noise ratio is related to the integration time (TINT) and the integration time constant (RINT) (CINT) as follows:
EQUATION 7-1:
S/N (dB) = 20 Log
( 30 xIN10-6 * (RINT)INT(CINT)) *
V
t
The length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. The calculation of TINT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a defined state.
7.5
Reference De-integration
7.2
System Timing
To obtain maximum performance from the TC5XX, the overshoot at the end of the De-integration phase must be minimized. Also, the Integrator Output Zero phase must be terminated as soon as the comparator output returns high. (See Figure 4-1). Figure 4-1 shows the overall timing for a typical system in which a TC5XX is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output, CMPTR, using an I/O line or dedicated timer capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference De-integration phase. (This is further explained below.) The timing diagram in Figure 4-1 is not to scale, as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 4-1): sampling the input polarity; capturing the de-integration time; minimizing overshoot and properly executing the Integrator Output Zero phase.
The length of this phase must be precisely measured from the transition of AB from 10 to 11 to the falling edge of CMPTR. The comparator delay contributes some error in timing this phase. The typical delay is specified to be 2sec. This should be considered in the context of the length of a single count when determining overall system performance and possible single count errors. Additionally, Overshoot will result in charge accumulating on the integrator after its output crosses zero. This charge must be nulled during the Integrator Output Zero phase.
7.3
Auto Zero Phase
The length of this phase is usually set to be equal to the Input Signal Integration time. This decision is virtually arbitrary since the magnitudes of the various system errors are not known. Setting the Auto Zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefinitely (i.e., Auto Zero is the appropriate Idle state for a TC5XX device).
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DS21428B-page 12
2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 7-1: NOISE THRESHOLD
S S 30 V S
NTH LowREF
NTH Normal VREF VREF N = Noise Threshold RINT CINT TH
NTH High VREF
Slope (S) =
7.6
Integrator Output Zero Phase
7.7
7.7.1
Using the TC510/TC514
NEGATIVE SUPPLY VOLTAGE CONVERTER (TC510, TC514)
The comparator delay and the controller's response latency may result in overshoot, causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The Integrator Output Zero phase should be activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately so that Overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the integrator is near zero. Auto Zero should be entered (AB = 01) and the TC5XX held in this state until the next cycle is begun (see Figure 7-2).
A capacitive charge pump is employed to invert the voltage on VDD for negative bias within the TC510/TC514. This voltage is also available on the VOUT- pin to provide negative bias elsewhere in the system. Two external capacitors are required to perform the conversion. Timing is generated by an internal state machine driven from an on-board oscillator. During the first phase, capacitor CF is switched across the power supply and charged to VS+. This charge is transferred to capacitor COUT- during the second phase. The oscillator normally runs at 100kHz to ensure minimum output ripple. This frequency can be reduced by placing a capacitor from OSC to VDD. The relationship between the capacitor value is shown in Section 9.0.
FIGURE 7-2:
Integrator Output
OVERSHOOT
Zero Crossing
7.7.2
Overshoot Comparator Output Comp Integrate Phase De-integrate Phase Integrator Zero Phase
ANALOG INPUT MULTIPLEXER (TC514)
The TC514 is equipped with a four input differential analog multiplexer. Input channels are selected using select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00).
2002 Microchip Technology Inc.
DS21428B-page 13
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TC500/A/510/514
8.0 DESIGN EXAMPLE (SEE FIGURES 8-1 TO 8-4)
Given: Required Resolution: (16 Bits (65,536 counts). Maximum V IN: 2V Power Supply Voltage: +5V 60Hz System Step 1: Pick integration time (tINT) as a multiple of the line frequency: 1/60Hz = 16.6msec. Use 4x line frequency = 66msec Step 2: Calculate RINT RINT = VIN(MAX) /20A 2 /20A = 100k Step 3: Calculate CINT for maximum (4V) integrator output swing: C INT = (tINT) (20 x 10 -6) / (V S - 0.9) = (.066) (20 x 10 -6) / (4.1) = .32F (use closest value: 0.33F) Note: Microchip recommended capacitor: Evox-Rifa p/n: 5MR5 334K50J03L4. rate: Conversions/sec: = 1/(TAZ + TINT + 2 TINT + 2msec) = 1/(66msec +66msec +132msec +2msec) = 3.7 conversions/sec From which CAZ = CREF = 0.22F (see Table 6-1) Note: Microchip recommended capacitor: Evox-Rifa p/n: 5MR5 224K50J02L4
Step 4: Choose CREF and C AZ based on conversion
Step 5: Calculate V REF EQUATION 8-1:
VREF = (V S - 0.9) (C INT) (RINT) 2(TINT) = (4.1) (0.33 x 1 -6) (105) / 2(.066) = 1.025V
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DS21428B-page 14
2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 8-1: TC510 DESIGN SAMPLE
1 1F CINT 0.33F CAZ 0.22F +5V RINT 100k MCP1525 2 VOUTCINT CAPDGND 24 23 1F +5V Typical Waveforms Pin 2 +5V Microcontroller CMPTR A B 19 18 VIN17 INPUT+ INPUT- Pin 19 Pin 2 VIN+ Pin 19
3 4
TC510
CAZ BUF
CAP+ 22 VDD 21
5 ACOM 6 CREFCREF+
CREF R2 0.22F 10k R3, 10k C1 0.01F
7
1F
9V REF8 VREF+
VIN+ 16 VIN- 15
FIGURE 8-2:
TC514 DESIGN EXAMPLE
1 CINT 1F 0.33F CAZ 0.22F +5V RINT 100k MCP1525 10k 1F 10k C1, .01F CREF 0.22F 2
VOUTCINT CAZ BUF
CAPDGND
28 27 26 25 22 19 23 Analog Mux Logic Microcontroller +5V
1F
+ 5V
3 4
CAP+
TC514
VDD A0 A1
5 ACOM 6C REF7C REF+ 9 8 VREFVREF+
CMPTR
A 22 B 21 CH1+ CH1- 18 13 INPUT 1+ INPUT 1- Typical Waveforms CH2+ 17 CH2- 12 CH3+ 16 CH3- 11 CH4+ 15 CH4- 10 INPUT 2+ INPUT 2- VIN+ INPUT 3+ INPUT 3- INPUT4+ INPUT4- PIN 2 VIN PIN 23 PIN 23 PIN 2
2002 Microchip Technology Inc.
DS21428B-page 15
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TC500/A/510/514
FIGURE 8-3: TC510 TO IBM(R) COMPATIBLE PRINTER PORT
+5V 21 VDD 1 VOUTCAPCAP+ CREF+ 0.22F CREFVREF+ 6 9 10k 0.01F VREFPC Printer Port PORT 0378 HEX 8 4 3 2 16 15 5 100k 0.22F 0.33F 100k + 0.01F Input - DGND 23 ACOM 1F 10k MCP1525 24 1F 22 7 1F
TC510
BUF 2 3 10 18 17 19 A B CMPTR CAZ CINT VIN+ VIN-
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DS21428B-page 16
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TC500/A/510/514
FIGURE 8-4: TC514 TO IBM COMPATIBLE PRINTER PORT
+5V 25 18 CH1+ VDD 1 VOUT
-
+ Input 1 - + Input 2 - + Input 3 - + Input 4 -
28 CAP-
1F 1F
13 CH1- 17 12 16 11 15 CAP+ CH2+ CH2- CH3+ CREFCH3- CH4+ CREF+
26
10k
7 0.22F 6 10k
MCP1525
VREF+ 9
10k 0.01F
10 CH4- 20
TC514
VREF8
A0 A1 A B CMPTR 100k
Analog Mux Control Logic IBM Printer Port Port 0378 Hex
19 22 21 23
BUF CAZ CINT
4 3 2
2 3 10
0.22F
0.33F
ACOM
5
DGND 27
2002 Microchip Technology Inc.
DS21428B-page 17
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TC500/A/510/514
9.0 TYPICAL CHARACTERISTICS
The graphs and tables following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range), and therefore outside the warranted range.
Output Voltage vs Load Current 5 4 Output Voltage (V) 3 2 1 0 -1 -2 -3 -4 -5 0
Slope 60
Output Voltage vs. Output Current -0 -1
Output Voltage (V)
TA = 25C
TA = 25C V+ = 5V
-2 -3 -4 -5 -6 -7 -8
10
20
30 40 60 50 Load Current (mA)
70
80
0
2
4
6 8 10 12 14 16 Output Current (mA)
18 20
Output Ripple vs. Load Current
Output Source Resistance (W)
Output Source Resistance vs. Temperature 100 90 80 70 60 50 40 -50
V+ = 5V IOUT = 10mA
200
Output Ripple (mV PK-PK)
175 150 125 100 75 50 25 0 0
V+ = 5V, TA = 25C Osc. Freq. = 100kHz
CAP = 1F
CAP = 10F
1
2
3
4 5 6 7 Load Current (mA)
8
9 10
-25
0 25 50 Temperature (C)
75
100
Oscillator Frequency vs. Capacitance 100
Oscillator Frequency (kHz)
Oscillator Frequency (kHz)
TA = +25C V+ = 5V
Oscillator Frequency vs. Temperature 150
V+ = 5V
125
10
100
75 50 -50
1 1 10 100 Oscillator Capacitance (pF) 1000
-25
0
25 75 50 Temperature (C)
100
125
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DS21428B-page 18
2002 Microchip Technology Inc.
TC500/A/510/514
10.0
10.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
10.2
Taping Forms
Component Taping Orientation for 16-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
16-Pin SOIC (W)
16 mm
12 mm
1000
13 in
Component Taping Orientation for 24-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
24-Pin SOIC (W)
24 mm
12 mm
1000
13 in
2002 Microchip Technology Inc.
DS21428B-page 19
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TC500/A/510/514
10.2 Taping Forms (Continued)
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
28-Pin SOIC (W)
24 mm
12 mm
1000
13 in
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DS21428B-page 20
2002 Microchip Technology Inc.
TC500/A/510/514
10.3 Package Dimensions
16-Pin PDIP (Narrow)
PIN 1
.270 (6.86) .240 (6.10)
.045 (1.14) .030 (0.76) .770 (19.56) .740 (18.80) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .310 (7.87) .290 (7.37)
.040 (1.02) .020 (0.51)
.014 (0.36) .008 (0.20) .400 (10.16) .310 (7.87)
10 MAX.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.022 (0.56) .015 (0.38) Dimensions: inches (mm)
16-Pin SOIC (Narrow)
PIN 1
.157 (3.99) .150 (3.81)
.244 (6.20) .228 (5.79)
.050 (1.27) TYP
.394 (10.00) .385 (9.78) .069 (1.75) .053 (1.35) .018 (0.46) .014 (0.36) .010 (0.25) .004 (0.10)
8 MAX. .050 (1.27) .016 (0.40)
.010 (0.25) .007 (0.18)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21428B-page 21
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TC500/A/510/514
10.3 Packaging Dimensions (Continued)
16-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65) .291 (7.40) .398 (10.10)
.413 (10.49) .398 (10.10) .104 (2.64) .097 (2.46) .050 (1.27) TYP. .019 (0.48) .014 (0.36) .012 (0.30) .004 (0.10)
8 MAX. .050 (1.27) .016 (0.40)
.013 (0.33) .009 (0.23)
Dimensions: inches (mm)
24-Pin PDIP (Narrow)
PIN 1
.280 (7.11) .240 (6.10)
.045 (1.14) .030 (0.76) 1.195 (30.35) 1.155 (29.34) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .310 (7.87) .290 (7.37)
.040 (1.02) .015 (0.38)
.015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87)
3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.023 (0.58) .015 (0.38)
Dimensions: inches (mm)
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DS21428B-page 22
2002 Microchip Technology Inc.
TC500/A/510/514
10.3 Packaging Dimensions (Continued)
24-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65) .291 (7.40) .398 (10.10)
.615 (15.62) .597 (15.16) .104 (2.64) .097 (2.46) .012 (0.30) .004 (0.10)
8 MAX. .050 (1.27) .016 (0.40)
.013 (0.33) .009 (0.23)
.050 (1.27) TYP. .019 (0.48) .014 (0.36)
Dimensions: inches (mm)
28-Pin PDIP (Narrow)
PIN 1
.288 (7.32) .240 (6.10)
.045 (1.14) .030 (0.76) .310 (7.87) .290 (7.37)
1.400 (35.56) 1.345 (34.16) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92)
.040 (1.02) .015 (0.38)
.015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87)
3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.022 (0.56) .015 (0.38)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21428B-page 23
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TC500/A/510/514
10.3 Package Dimensions (Continued)
28-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65) .291 (7.40) .398 (10.10)
.713 (18.11) .697 (17.70) .103 (2.62) .097 (2.46) .019 (0.48) .014 (0.36) .012 (0.30) .004 (0.10)
8 MAX. .050 (1.27) .016 (0.40)
.013 (0.33) .009 (0.23)
Dimensions: inches (mm)
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DS21428B-page 24
2002 Microchip Technology Inc.
TC500/A/510/514
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21428B-page 25
TC500/A/510/514
NOTES:
DS21428B-page 26
2002 Microchip Technology Inc.
TC500/A/510/514
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21428B-page 27
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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ASIA/PACIFIC
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04/20/02
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DS21428B-page 28
2002 Microchip Technology Inc.
*B82412SD*

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